PCB Design: What is the minimum via drill size for a given trace width?

A screenshot of KiCad PCB design software showing one of the author’s work in progress.

The current-carrying abilities of a trace is well understood, but what about vias?

One way of seeing it is to size the trace appropriately first, then consider its copper cross-section, and maintain that cross-section through the via. Read on…

Back-of-the-envelope estimations based on 70μm copper (2oz) and 25μm hole plating thickness (1mil) shows the via drill diameter should roughly be greater or equal to the trace width it connects to, in order to maintain the copper section through the hole.

When using 35μm copper (1oz) the via drill hole should be greater or equal than half the trace width.

Some fabs say the plating can be as thin as 16μm in their vias, and in that case the minimum via drill hole should be 1.5 * trace width for 2oz copper layers and 0.75 * trace width for 1oz copper, just to avoid introducing a current restriction.

Here is Axel’s rule of thumb for via drill holes, that is a safe default erring on the side of caution in all situations: “the via’s drill diameter should be 1.5 times the trace’s width”. This probably means larger vias that many people use.

Advanced users can use the following formulas to estimate the minimum via drill and pad diameters matching their traces:

via_drill_diameter = via_plating_thickness + trace_width * copper_layer_thickness / (pi * via_plating_thickness)

and

via_pad_diameter = via_drill_diameter + trace_width

to get the minimum via drill diameter and pad dimensions that maintain the copper cross-section in all directions given the trace width, the copper layer thickness, and the minimum plating thickness inside vias as declared by their fab.

This is of course an estimation base strictly on conductor geometry, that is assuming the plating in the holes has the same electrical characteristics as the layer material.

Smart software could auto-pick suitable via dimensions based on those simple formulas, considering the thickest layer the via is interconnecting, and the trace width on that layer, and also pick a via crown width that is at least 0.5 times the trace width to ensure…